Table of Contents Chapter 1 Using FPGA Express with VHDL . 1-1 Hardware Description Languages . 1-1 Typical Uses for HDLs 1-1 Advantages of HDLs 1-2 About VHDL 1-2 FPGA Express Design Process . 1-4 Using FPGA Express to Compile a VHDL Design . 1-4 Design Methodology . 1-4 Chapter 2 Description Styles 2-1 Design Hierarchy . 2-1 Data Types 2-2 Design Constraints 2-2 Register Selection 2-2 Asynchronous Designs 2-2 Language Constructs 2-3 Chapter 3 Describing Designs . 3-1 VHDL Entities . 3-1 VHDL Constructs . 3-3 Entities 3-3 Architectures 3-5 Configurations 3-6 Processes . 3-6 Subprograms 3-7 Packages 3-8 Using a Package 3-8 Package Structure 3-9 Package Declarations . 3-9 Package Bodies 3-10 Defining Designs 3-11 Entity Specifications . 3-11 Entity Generic Specifications 3-12 Entity Port Specifications 3-12 Entity Architectures 3-13 Entity Configurations 3-16 Subprograms 3-17 Subprogram Declarations . 3-17 Subprogram Bodies 3-19 Subprogram Overloading . 3-20 Operator Overloading . 3-21 Type Declarations 3-21 Subtype Declarations . 3-21 Constant Declarations 3-22 Signal Declarations 3-22 Resolution Functions 3-22 Variable Declarations . 3-25 Structural Design . 3-25 Using Hardware Components 3-26 Component Declaration 3-26 Sources of Components . 3-27 Consistency of Component Ports . 3-27 Component Instantiation Statement . 3-27 Mapping Generic Values 3-28 Mapping Port Connections . 3-29 Technology-Independent Component Instantiation 3-30 Chapter 4 Data Types . 4-1 Enumeration Types . 4-2 Enumeration Overloading . 4-3 Enumeration Encoding . 4-3 Enumeration Encoding Values . 4-4 Integer Types 4-5 Array Types . 4-5 Constrained Array 4-6 Unconstrained Array . 4-6 Array Attributes . 4-7 Record Types . 4-8 Predefined VHDL Data Types . 4-9 Data Type BOOLEAN 4-11 Data Type BIT 4-11 Data Type CHARACTER . 4-11 Data Type INTEGER 4-11 Data Type NATURAL . 4-11 Data Type POSITIVE . 4-11 Data Type STRING 4-12 Data Type BIT_VECTOR . 4-12 Unsupported Data Types 4-12 Physical Types . 4-12 Floating Point Types . 4-12 Access Types . 4-12 File Types . 4-12 SYNOPSYS Data Types . 4-12 Subtypes . 4-12 Chapter 5 Expressions 5-1 Operators 5-2 Logical Operators . 5-3 Relational Operators 5-4 Adding Operators . 5-5 Unary (Sign) Operators 5-8 Multiplying Operators . 5-8 Miscellaneous Arithmetic Operators . 5-10 Operands . 5-11 Operand Bit Width 5-12 Computable Operands . 5-12 Literals 5-14 Numeric Literals 5-14 Character Literals . 5-15 Enumeration Literals . 5-15 String Literals 5-15 Identifiers 5-16 Indexed Names 5-17 Slice Names . 5-18 Limitations on Null Slices 5-19 Limitations on Noncomputable Slices . 5-20 Records and Fields 5-20 Aggregates . 5-21 Attributes 5-22 Function Calls . 5-22 Qualified Expressions . 5-23 Type Conversions 5-24 Chapter 6 Sequential Statements 6-1 Assignment Statements 6-2 Assignment Targets . 6-2 Simple Name Targets . 6-2 Indexed Name Targets . 6-3 Slice Targets 6-4 Field Targets 6-5 Aggregate Targets 6-6 Variable Assignment Statement 6-7 Signal Assignment Statement . 6-7 Variable Assignment 6-7 Signal Assignment 6-7 if Statement . 6-8 Evaluating condition . 6-9 Using the if Statement to Imply Registers and Latches 6-9 case Statement . 6-10 Using Different Expression Types 6-10 Invalid case Statements . 6-12 loop Statements . 6-13 loop Statement . 6-14 while loop Statement . 6-14 for loop Statement . 6-14 next Statement . 6-16 exit Statement . 6-18 Subprograms 6-19 Subprogram Calls . 6-20 Procedure Calls 6-21 Function Calls . 6-23 return Statement 6-24 Mapping Subprograms to Components (Entities) 6-24 wait Statement 6-29 Inferring Synchronous Logic . 6-29 Combinational vs. Sequential Processes . 6-33 null Statement 6-34 Chapter 7 Concurrent Statements 7-1 process Statements . 7-2 Combinational Process Example . 7-3 Sequential Process Example . 7-4 Driving Signals . 7-5 block Statement . 7-6 Concurrent Procedure Calls . 7-7 Concurrent Signal Assignments . 7-9 Conditional Signal Assignment . 7-10 Selected Signal Assignment . 7-11 Component Instantiations 7-13 generate Statements . 7-15 for generate Statement 7-15 if generate Statement 7-17 Chapter 8 Register and Three-State Inference . 8-1 Register Inference 8-1 Using Register Inference 8-2 Describing Clocked Signals 8-2 wait vs if Statements . 8-3 Recommended Use of Register Inference Capabilities 8-4 Restrictions on Register Capabilities 8-5 Delays in Registers 8-6 Describing Latches . 8-7 Automatic Latch Inferencing . 8-8 Restrictions on Latch Inference Capabilities 8-9 Example—Design with Two-Phase Clocks 8-10 Describing Flip-Flops 8-11 Flip-Flop with Asynchronous Reset 8-11 Example—Synchronous Design with Asynchronous Reset . 8-12 Attributes 8-14 async_set_reset . 8-14 Latch with Asynchronous Set or Clear Inputs . 8-14 sync_set_reset . 8-15 Flip-Flop with Synchronous Reset Input . 8-15 async_set_reset_local 8-16 sync_set_reset_local 8-18 async_set_reset_local_all 8-20 sync_set_reset_local_all 8-22 one_hot . 8-24 one_cold . 8-26 FPGA Express Latch and Flip-Flop Inference 8-28 Efficient Use of Registers . 8-29 Example—Using Synchronous and Asynchronous Processes 8-31 Three-State Inference 8-33 Assigning the Value Z 8-34 Latched Three-State Variables . 8-35 Chapter 9 FPGA Express Directives 9-1 Notation for FPGA Express Directives . 9-1 FPGA Express Directives . 9-1 Translation Stop and Start Directives . 9-2 Resolution Function Directives . 9-4 Component Implication Directives 9-4 Chapter 10 Synopsys Packages 10-1 std_logic_1164 Package . 10-1 std_logic_arith Package . 10-2 Using the Package . 10-2 Modifying the Package . 10-3 Data Types . 10-4 UNSIGNED . 10-4 SIGNED 10-4 Conversion Functions . 10-5 Arithmetic Functions . 10-7 Comparison Functions . 10-10 Shift Functions 10-12 Multiplication Using Shifts . 10-13 ENUM_ENCODING Attribute . 10-14 pragma built_in . 10-14 Two-Argument Logic Functions 10-14 One-Argument Logic Functions 10-15 Type Conversion 10-16 translate_off Directive . 10-16 std_logic_misc Package . 10-17 Chapter 11 HDL Constructs 11-1 VHDL Construct Support 11-1 Design Units . 11-2 Data Types . 11-2 Declarations . 11-3 Specifications . 11-4 Names 11-4 Operators . 11-5 Operands and Expressions 11-5 Sequential Statements . 11-6 Concurrent Statements 11-7 Predefined Language Environment 11-8 VHDL Reserved Words . 11-9 Index . Index-1 VHDLman
