Tài liệu the PCI Bus demystified phần 5

This parameter is to be interpreted as the cumulative edge rate across
the specified range, rather than the instantaneous rate at any point
within the transition range. The specified load (Figure 5-5) is optional;
i.e., the designer may elect to meet this parameter with an unloaded
output per revision 2.0 of the PCI Local Bus Specification. However,
adherence to both maximum and minimum parameters is now required
(the maximum is no longer simply a guideline). Since adherence to
the maximum slew rate was not required prior to revision 2.1 of the
specification, there may be components in the market for some time
that have faster edge rates; therefore, motherboard designers must bear
in mind that rise and fall times faster than this specification could
occur, and should ensure that signal integrity modeling accounts for
this. Rise slew rate does not apply to open drain outputs.