Tài liệu the PCI Bus demystified phần 2

Target Ready indicates that the selected target device
is able to complete the current data phase. During a read, TRDY#
indicates that valid data is present on AD[31::0]. During a write,
it indicates that the target is prepared to accept data. A data phase
completes on any clock cycle during which both IRDY# and TRDY#
are asserted. (s/t/s)