Thạc Sĩ FPGA (Feld Programmable Gate Array) Based design and implementation for optical transport networks

UNIVERSITY OF SCIENCE
Master Thesis in Electronic Engineering
2010


TABLE OF CONTENTS
ABSTRACT 2


CHAPTER 1 : INTRODUCTION 9
1.1 Introduction 9
1.2 Project objectives 11
1.3 Project scope . 11
1.4 Thesis outline 12


CHAPTER 2 : FPGA AND HDL CHIP DESIGN . 14
2.1 Introduction 14
2.2 FPGA architecture overview . 15
2.3 Stratix II FPGA 17
2.4 Hardware description language 21
2.4.1 Introduction 21
2.4.2 Verilog HDL Structure 22


CHAPTER 3 : PRINCIPLES AND APPLICATIONS OF OPTICAL COMMUNICATIONS . 30


3.1 Optical fiber communication technology . 30
3.2 System overview, trends and advances . 34
3.3 Standard and devices requirements 37
3.3.1 Standard . 37
3.3.2 Devices requirements 41


CHAPTER 4 : FPGA-BASED DESIGN AND IMPLEMENTATION . 47


4.1 Overview of the design 47
4.2 Software design 51
4.3 Hardware design . 52
4.3.1 High speed 8B/10B Encoder and Decoder Design . 66
4.3.2 Details of the Encoding Process 67
4.3.3 FIFO Functionality 72
4.4 Download the design into hardware 78


CHAPTER 5 : SIMULATION RESULTS AND EXPERIMENTAL TESTS ON FPGA CHIPS . . 80


5.1 Introduction 80
5.2 Individual component test 80
5.2.1 8B/10B encoder and decoder implemetation and
simulation results 80
5.2.2 FIFO Implemetation and simulation results 86
5.2.3 System compilation 93
5.2.4 Breadboard prototype test . 94
5.3 System level testing for transmitter and receiver . 97
5.3.1 Optical link test 97
5.3.2 Gigabit Ethernet test 97


CHAPTER 6 : CONCLUSION AND FUTURE WORK . 100


6.1 Conclusion . 100
6.2 Future work 101
REFERENCES . 102



List of Figures
Figure 2.1: Structure of an FPGA. . 15
Figure 2.2: SRAM-controlled Programmable Switches. 16
Figure 2.3 : Actel Antifuse Structure. 17
Figure 2.4: Top view Stratix II. 18
Figure 2.5: Stratix II Block Diagram. . 19
Figure 2.6: 1,020-PIN FPGA Package Outline 20
Figure 2.7: Verilog . 21
Figure 3.1: Optical transmitter and receiver. . 31
Figure 3.2: Fiber to the X (FTTX) 33
Figure 3.3: Enterprise LAN Topology 33
Figure 3.4: Today’s networks 34
Figure 3.5: Total Traffic Bandwidth Increases . 35
Figure 3.6: Convergence of Ethernet and Optical transports 35
Figure 3.7: Overview of optical transport networks . 36
Figure 3.8: Relationship of IEEE 802.3 layering model to OSI reference model 39
Figure 3.9: SPLC-20-4-X-BX . 41
Figure 3.10: Diagram of host board connector block pin numbers and names . 42
Figure 3.11: Block diagram of SFP . 44
Figure 3.12: Single-mode fiber and multimode fiber . 45
Figure 3.13: HDMP-1636A/46A/T1636A transceiver 46
Figure 4.1: Design flow using Quartus II . 48
Figure 4.2: Design flow . 48
Figure 4.3: Full IC Design Flow . 51
Figure 4.4: Quartus II Software Basic Design Flow 52
Figure 4.5: Stratix II block diagram . 54
Figure 4.6: Top-level block diagram of the system . 55
Figure 4.7: FPGA Stratix II 56
Figure 4.8: Block diagram of Gigabit Ethernet 57
Figure 4.9: Block diagram of MAC 57
Figure 4.10: MAC control frame format . 58
Figure 4.11: Format of frame preamble 59
Figure 4.12: Shift register generating CRC-8 60
Figure 4.13: Functional block diagram 65
Figure 4.14: The 8B/10B Encoder and decoder in a system stransmission . 66
Figure 4.15: The 8B/10B coding scheme 67
Figure 4.16: State machine of running disparity . 71
Figure 4.17: First-in, first-out functionality gives a FIFO register file a specific directionality . 72
Figure 4.18: A typical block diagram of a synchronous FIFO 74
Figure 4.19: The illustrative examples of FIFO occupancy. . 75
Figure 4.20: A typical block diagram of a asynchronous FIFO . 76
Figure 4.21: FIFO state machine transition diagram. 77
Figure 4.22: FPGA daughter board 78
Figure 4.23: AT FPGA mother board and daughter board 79
Figure 4.24: The Gigabit Ethernet fibre optical connection . 79
Figure 5.1: Encoder Block Diagram 81
Figure 5.2: Decoder Block Diagram 81
Figure 5.3: Schemetic Symbol of an 8B10B Encoder . 82
Figure 5.4: Schemetic Symbol of an 8B10B Decoder . 83
Figure 5.5: Encoder 8B10B Timing Diagrams . 85
Figure 5.6: Decoder 8B10B Timing Diagrams 85
Figure 5.7: Schemetic Symbol of an Asynchronous FIFO 87
Figure 5.8: Initial write operations to an FIFO. 91
Figure 5.9: Read and Write Operations to an Almost Full FIFO . 92
Figure 5.10: Read and Write Operations to an almost empty FIFO 93
Figure 5.11: Full compilation was successful report . 93
Figure 5.12: Linux System login 94
Figure 5.13: Load FPGA and show status 94
Figure 5.14: Data receive after sending messages . 95
Figure 5.15: Show data in buffer . 95
Figure 5.16: Clear data in buffer . 96
Figure 5.17: The connection was tested. 96
Figure 5.18: The disconnection was tested. 96
Figure 5.19: System connection test with telnet 97
Figure 5.20: Wireshark Preferences . 98
Figure 5.21: Wireshark Options 98
Figure 5.22: Command window 99
Figure 5.23: The sent packet and the received packet . 99




List of Tables
Table 2.1: Stratix II FPGA EP2S180 features . 18
Table 3.1: Ethernet Communication Standards 37
Table 3.2: Common Fiber Optic Attachment options for standard 802.3z 38
Table 3.3: Diagram of Host Board Connector Block Pin Numbers and Names 43
Table 4.1: 3-bit to 4-bit Encoding Values 69
Table 4.2: 5-bit to 6-bit Encoding Values 69
Table 4.3: 8B/10B encoding/decoding mapping table . 70



CHAPTER 1: INTRODUCTION
his chapter introduces the motivation and objectives of this thesis about the optical transport implementation based on Field Programmable Gate Array. Description on the available hardware for implementation is presented. The problem statement of the project will also be carried out in this thesis. The outline of the thesis is provided.


1.1 Introduction
Recently, there has been a great demand of the high-speed data transmission due to the emerging applications in digital communications such as high quality audio, video transmission [5], [12]. The development of technology which can support the high data rate transmission of various applications is of considerable interest. Among the advanced transmission technologies, the optical fiber systems are the suitable choice due to their potential advantages. The optical transport networks enable to transmit more information than conventional cable networks. In addition, the advances of signal processing techniques allow to implement the hardware for the high-speed data transmission efficiently.
There are several methods to implement the system. One of the methods to implement the system is using FPGAs (Field Programmable Gate Arrays). FPGAs are the fastest, smallest, and shortest way to implement into hardware. This method is flexibility of design process and the shorter time to market for the chip design [4],[18].


The disadvantages of using this hardware are it needs memory and other peripheral chips to support the operation. Besides that, it uses the most power usage and memory space, and would be the slowest in terms of time to produce the output compared to other hardwares.
FPGA is an example of VLSI circuit which consists of a “sea of NAND gates” whereby the function are customer provided in a “wire list”. This hardware is programmable and the designer has full control over the actual design implementation without the need and delay for any physical IC fabrication facility. An FPGA combines the speed, power, and density attributes of an ASIC with the programmability of a general purpose processor will give advantages to the optical transport system.


An FPGA could be reprogrammed for new functions by a base station to meet future needs particularly when new design is going to fabricate into chip. This will be the best choice for optical transport implementation since it gives flexibility to the program design besides the low cost hardware component compared to others.


As the performance of optical networks increases, optical network interface will have a significant