Thạc Sĩ Fpga-based design and implementation for optical transport networks

ABSTRACT

The thesis presents an approach to system design and implementation for optical transport networks. The design of the system based on the Field Programmable Gate Array (FPGA) and Gigabit optical network is discussed. Gigabit optical network interfaces provide fixed functionality and are optimized for sending and receiving large packets. All modules are designed using Verilog Hardware Description Language (HDL) and implemented using AT FPGA board version 1.0. The board is connected to computer and Quartus II Version 8.0 is used to design, compile and implement for the hardware. All processing is executed in AT FPGA version 1.0 board and only requires the input data to the hardware throughout interfaces. To test and analyse results, input and output data are displayed to computer, and the results are compared using HyperTerminal or Telnet command. Softwares and tools used in this project include Verilog HDL Design Entry Altera Quartus II 8.0. Some software tools are used to assist the design
process and downloading process into Altera FPGA chip Stratix II EP2S180, while AT FPGA board version 1.0 is used to implement the designed module. The experimental results at Gigabit Ethernet receiving interface indicate that the optical interface can receive all packet sizes and store them in SDRAM at Gigabit Ethernet line rate.
TABLE OF CONTENTS

ABSTRACT 2
CHAPTER 1 : INTRODUCTION 9
1.1 Introduction 9
1.2 Project objectives 11
1.3 Project scope . 11
1.4 Thesis outline 12
CHAPTER 2 : FPGA AND HDL CHIP DESIGN . 14
2.1 Introduction 14
2.2 FPGA architecture overview . 15
2.3 Stratix II FPGA 17
2.4 Hardware description language 21
2.4.1 Introduction 21
2.4.2 Verilog HDL Structure 22
CHAPTER 3 : PRINCIPLES AND APPLICATIONS OF OPTICAL
COMMUNICATIONS . 30
3.1 Optical fiber communication technology . 30
3.2 System overview, trends and advances . 34
3.3 Standard and devices requirements 37
3.3.1 Standard . 37
3.3.2 Devices requirements 41
CHAPTER 4 : FPGA-BASED DESIGN AND IMPLEMENTATION . 47
4.1 Overview of the design 47
4.2 Software design 51
4.3 Hardware design . 52
4.3.1 High speed 8B/10B Encoder and Decoder Design . 66
4.3.2 Details of the Encoding Process 67
4.3.3 FIFO Functionality 72
4.4 Download the design into hardware 78
CHAPTER 5 : SIMULATION RESULTS AND EXPERIMENTAL TESTS ON
FPGA CHIPS 80
5.1 Introduction 80
5.2 Individual component test 80
5.2.1 8B/10B encoder and decoder implemetation and
simulation results 80
5.2.2 FIFO Implemetation and simulation results 86
5.2.3 System compilation 93
5.2.4 Breadboard prototype test . 94
5.3 System level testing for transmitter and receiver . 97
5.3.1 Optical link test 97
5.3.2 Gigabit Ethernet test 97
CHAPTER 6 : CONCLUSION AND FUTURE WORK . 100
6.1 Conclusion . 100
6.2 Future work 101
REFERENCES . 102