Sách DSP Builder Handbook Volume 3 DSP Builder Advanced Blockset

DSP Builder Handbook
Volume 3: DSP Builder Advanced Blockset


Contents
Section I. DSP Builder Advanced Blockset User Guide
Chapter 1. About the DSP Builder Advanced Blockset
Architecture versus Implementation . 1–1
Libraries . 1–2
Base Blocks . 1–2
FFT Blockset . 1–2
ModelBus Blocks 1–3
ModelPrim Blocks 1–3
ModelIP Blocks . 1–3
Cycle Accuracy and Latency 1–3
Sample Rate and Clocks 1–4
Interoperability with the Standard Blockset . 1–4
Learning to Use the Advanced Blockset 1–4
Chapter 2. Design Flow
Introducing a DSP Builder Design . 2–1
Signals Block . 2–2
Control Block . 2–3
Device Block . 2–3
SynthesisInfo Block . 2–4
Other Blocks . 2–4
Typical Design Flow . 2–4
Implementing your Design . 2–6
Staging your Design into Subsystems 2–6
Choosing the ModelIP Library or the ModelPrim Library 2–7
Using ModelPrim Blocks . 2–7
Specifying the Output Data Type . 2–8
SynthesisInfo Block . 2–9
Loops . 2–9
Using Vectors . 2–10
Using ModelPrim Blocks Outside ModelPrim Subsystems 2–11
Using Interfaces as Subsystem Boundaries 2–12
Using Interfaces as Scheduling Boundaries 2–12
Connecting Blocks . 2–12
Connecting Subsystems 2–15
Building Multichannel Systems 2–20
Channel, Data, Valid Examples 2–20
Using Vectorized Inputs 2–22
Verify the Design in Simulink and MATLAB . 2–23
Using References . 2–23
Setting up Stimulus 2–23
Analyzing your Design . 2–23
Exploring Design Tradeoffs 2–24
Managing Bit Growth 2–24
Implementing Rounding and Saturation 2–24
Using Convert Blocks and Specifying Output Types 2–25
Verifying and Debugging . 2–30
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Volume 3: DSP Builder Advanced Blockset
Running an Automatic Testbench 2–30
Simulating in the ModelSim Simulator 2–30
Integrating into Hardware . 2–30
Adding your Design to a Quartus II Project 2–33
Adding a DSP Builder Advanced Blockset Design to an Existing Quartus II Project . 2–33
Adding Advanced Blockset Components to Qsys 2–33
Guidelines . 2–33
Essential Guidelines 2–33
Recommended Guidelines 2–34
Chapter 3. Getting Started
Setting Up Simulink . 3–1
Using a Design Example or Reference Design . 3–1
Using the DSP Builder Menu in Simulink . 3–1
Running Automatic Testbenches 3–3
Chapter 4. ModelIP Tutorial
Creating a New Model From an Existing Design Example 4–1
Simulating, Verifying, and Compiling the Design 4–1
Reparameterizing the FIR Filter . 4–2
Doubling the Target Clock Rate . 4–3
Retargeting Design to Different Device Family 4–3
Chapter 5. ModelPrim Tutorial
The Fibonacci Design 5–1
Creating the Fibonacci Model . 5–1
Create a New Model 5–1
Add Blocks from the ModelPrim Library . 5–1
Create a Synthesizable Subsystem . 5–2
Complete the Top-Level Model . 5–3
Simulating the Design in Simulink . 5–4
Using Vector Types . 5–5
Using Complex Types . 5–6
Exploring the Generated Files 5–7
Simulating the RTL 5–7
Compiling with the Quartus II Software 5–7
Chapter 6. Design Examples and Reference Designs
Opening a Design Example . 6–1
Copying a Design Example . 6–2
Running a Design Example . 6–2
Base Blocks . 6–2
Scale 6–3
Local Threshold 6–3
FFT 6–3
1K Floating-Point FFT . 6–3
4K FFT 6–4
8K FFT 6–4
4K IFFT 6–5
8K IFFT 6–5
Radix 2 Streaming FFT . 6–6
Radix 4 Streaming FFT . 6–6
Variable-Size Low-Resource FFT 6–6
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Volume 3: DSP Builder Advanced Blockset
Filters 6–7
Decimating CIC Filter . 6–8
Decimating FIR Filter 6–8
Filter Chain with Forward Flow Control . 6–8
FIR Filter with Exposed Bus 6–8
Fractional FIR Filter Chain . 6–9
Fractional-Rate FIR Filter . 6–9
Half-Band FIR Filter . 6–9
Interpolating CIC Filter . 6–10
Interpolating FIR Filter . 6–10
Interpolating FIR Filter with Multiple Coefficient Banks . 6–10
Root-Raised Cosine FIR Filter 6–11
Single-Rate FIR Filter . 6–11
Super-Sample Decimating FIR Filter 6–12
Super-Sample Fractional FIR Filter . 6–12
Super-Sample Interpolating FIR Filter 6–12
Variable-Rate CIC Filter . 6–13
Folding . 6–13
Color Space Converter (Resource Sharing Folding) . 6–13
Position, Speed, and Current Control for AC Motors 6–14
Position, Speed, and Current Control for AC Motors (with ALU Folding) 6–19
Primitive FIR Filter (Resource Sharing Folding) 6–20
Single-Stage IIR Filter (Resource Sharing Folding) 6–20
Three-stage IIR Filter (Resource Sharing Folding) 6–21
Floating Point 6–21
Black-Scholes Floating Point . 6–22
Double-Precision Real Floating-Point Matrix Multiply 6–22
Fine Doppler Estimator . 6–22
Floating-Point Mandlebrot Set . 6–22
Single-Precision Complex Floating-Point Matrix Multiply . 6–24
Single-Precision Real Floating-Point Matrix Multiply . 6–25
Simple Nonadaptive 2D Beamformer . 6–25
Flow Control 6–25
Kronecker Tensor Product 6–26
Parallel Loops . 6–26
Primitive FIR with Back Pressure . 6–26
Primitive FIR with Forward Pressure . 6–27
Primitive Systolic FIR with Forward Flow Control 6–28
Rectangular Nested Loop . 6–29
Sequential Loops . 6–29
Triangular Nested Loop 6–29
Host Interface 6–29
Memory-Mapped Registers . 6–30
Platforms 6–30
16-Channel DDC . 6–30
16-Channel DUC . 6–31
2-Antenna DUC for WiMAX . 6–31
2-Channel DUC 6–32
Primitive Blocks 6–32
8×8 Inverse Discrete Cosine Transform . 6–33
Automatic Gain Control 6–33
Bit Combine for Boolean Vectors . 6–34
Bit Extract for Boolean Vectors . 6–34
Digital Predistortion Forward Path . 6–34
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Volume 3: DSP Builder Advanced Blockset
Fibonacci Series 6–35
Hello World . 6–35
Hybrid Direct Form and Transpose Form FIR Filter . 6–36
Loadable Counter 6–36
Matrix Initialization of LUT . 6–36
Matrix Initialization of Vector Memories 6–37
Multichannel IIR Filter 6–37
Quadrature Amplitude Modulation 6–38
Reinterpret Cast for Bit Packing and Unpacking 6–38
Run-time Configurable Decimating and Interpolating Half-Rate FIR Filter . 6–38
Test CORDIC Functions with Primitive Blocks . 6–38
Test CORDIC Functions with the CORDIC Block . 6–39
Vector Initialization of Sample Delay . 6–39
Wide Single-Channel Accumulators 6–40
Reference Designs 6–40
1-Antenna WiMAX DDC 6–41
2-Antenna WiMAX DDC 6–42
1-Antenna WiMAX DUC 6–42
2-Antenna WiMAX DUC 6–43
4-Carrier, 2-Antenna W-CDMA DDC . 6–44
1-Carrier, 2-Antenna W-CDMA DDC . 6–44
4-Carrier, 2-Antenna W-CDMA DUC . 6–45
1-Carrier, 2-Antenna W-CDMA DDC . 6–46
4-Carrier, 2-Antenna High-Speed W-CDMA DUC at 368.64 MHz with Total Rate Change 32 . 6–46
4-Carrier, 2-Antenna High-Speed W-CDMA DUC at 368.64 MHz with Total Rate Change 48 . 6–47
4-Carrier, 2-Antenna High-Speed W-CDMA DUC at 307.2 MHz with Total Rate Change 40 6–48
Cholesky Solver Single Channel 6–49
Cholesky Solver Multiple Channels 6–49
QR Decompostion . 6–50
Single-Channel 10-MHz LTE Transmitter . 6–50
STAP Radar Forward and Backward Substitution 6–51
STAP Radar Steering Generation . 6–52
STAP Radar QR Decomposition 192x204 6–52
Waveform Synthesis 6–52
Complex Mixer 6–52
Four Channel, Two Banks NCO 6–53
Four Channel, Four Banks NCO . 6–54
Four Channel, Eight Banks, Two Wires NCO 6–55
Four Channel, 16 Banks NCO 6–55
ModelIP 6–56
NCO . 6–56
NCO for HardCopy Devices . 6–57
NCO with Exposed Bus . 6–57
Real Mixer 6–57
Chapter 7. DDC Design Example Description
DDC Design Description . 7–1
Signals Block . 7–2
Control Block . 7–3
EditParams Blocks 7–3
Source Blocks . 7–3
Sink Blocks . 7–4
DDCChip Subsystem 7–4
Primary Inputs . 7–5
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Volume 3: DSP Builder Advanced Blockset
Merge Multiplexer 7–6
NCO 7–6
Mixer . 7–7
Mixer Scale Block . 7–7
DecimatingCIC and Scale Blocks 7–9
Decimating FIR Blocks . 7–10
Building the Design Example 7–13
Simulating the Design Example in Simulink . 7–13
Exploring the Generated Files . 7–14
Chapter 8. Floating-Point Data Types
Using Floating-Point Data Types 8–2
Converting Between Floating- and Fixed-Point Data Types . 8–2
Interacting with Other Features . 8–2
Folding 8–2
Pipelining Flexibility 8–2
Accuracy and Automatic Testbenches 8–3
Arithmetic Accuracy . 8–3
Floating-Point Format 8–4
Word Formats—Single Precision 8–4
Internal Floating Point Number—Single Precision . 8–4
Addition and Subtraction Format—Single Precision . 8–5
Multiplication and Division Format—Single Precision . 8–6
Double Precision Word Formats 8–6
Internal Floating Point Number—Double Precision 8–7
Addition and Subtraction Mantissa—Double Precision . 8–8
Multiplication and Division Format—Double Precision 8–8
Floating-Point Type Propagation 8–9
Special Considerations . 8–9
Flow Control 8–10
Floating-Point Design Examples 8–10
Chapter 9. DSP Builder Standard and Advanced Blockset Interoperability
Combined Blockset Example 1 9–2
Combined Blockset Example 2 9–6
Archiving Combined Blockset Designs 9–12
Advanced Blockset Example . 9–12
Chapter 10. Techniques for Experienced Users
Creating a New Model From an Existing Design Example 10–1
Managing your Designs . 10–2
Managing Basic Parameters . 10–3
Creating User Libraries . 10–3
Revision Control . 10–4
Creating Scripts 10–4
Writing Custom Scripts . 10–5
Folding . 10–7
ALU Folding 10–8
Inputs on Add and Mux Blocks . 10–10
Report File and The Resources in a Folded Design 10–11
Design Optimization 10–11
Vectors 10–13
Using ALU Folding . 10–13
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Testbenches 10–14
Using Automated Verification 10–14
Resource Usage Folding . 10–15
Time-Division Multiplexing 10–15
Enabling Resource Usage Folding . 10–17
Subsystem With Resource Usage Folding and Without Time Division Demultiplexing . 10–17
Subsystems With Resource Usage Folding and with Time Division Demultiplexing . 10–17
When to Use Resource Usage Folding . 10–19
Effects of Resource Usage Folding 10–19
Examples 10–22
Managing Latency . 10–22
Reading Latency 10–22
Using Latency Constraints . 10–23
Zero Latency Example . 10–25
Nonexplicit Delays 10–25
Distributed Delays 10–26
Latency and fMAX Constraint Conflicts . 10–28
Using Flow Control 10–29
Flow Control Using Latches 10–29
Forward Flow Control Using Latches 10–29
Flow Control Using FIFO Buffers . 10–30
Flow Control and Back Pressure Using FIFO Buffers . 10–30
Flow Control using Simple Loop 10–31
Flow Control Using the ForLoop Block . 10–31
Interfacing with a Processor Bus . 10–32
Assigning Base Address . 10–32
Integrating with Qsys . 10–32
Building System Components with Avalon-ST Interface Blocks . 10–33
Extending the Interface Definition 10–33
Adding More Ports to the Avalon-ST Blocks . 10–34
Adding Custom Text 10–34
Restrictions 10–34
Nios II Processor Example . 10–34
Chapter 11. Troubleshooting
Common Problems . 11–1
Timed Feedback Loops . 11–1
Loops, Clock Cycles and Data Cycles . 11–1
ModelPrim Subsystem Designs to Avoid 11–2
Section II. DSP Builder Advanced Blockset Libraries
Chapter 12. Additional Library
Avalon-ST Output (AStOutput) 12–1
Avalon-ST Input (AStInput) . 12–3
Avalon-ST Input FIFO Buffer (AStInputFIFO) 12–3
Nested Loops (NestedLoop1, NestedLoop2, NestedLoop3) 12–3
Operation . 12–4
Zero-Latency Latch (latch_0L) 12–5
Single-Cycle Latency Latch (latch_1L) . 12–6
Reset-Priority Latch (SRlatch_PS) . 12–6
Set-Priority Latch (SRlatch) 12–6
Expand Scalar (ExpandScalar) 12–7
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Vector Multiplexer (VectorMux) 12–7
Tapped Delay Line (TappedDelayLine) . 12–7
Chapter 13. Base Library
Channel Viewer (ChanView) . 13–1
Parameters 13–2
Port Interface 13–2
Updated Help . 13–2
Design Example . 13–3
Control . 13–3
Parameters 13–3
Hardware Generation 13–4
Memory-Mapped Bus Interface 13–4
Memory and Multiplier Trade-Off Options . 13–4
Updated Help . 13–6
Design Example . 13–6
Device 13–6
Design Example . 13–7
Edit Params . 13–7
Usage . 13–11
Design Example 13–11
LocalThreshold . 13–11
Parameters . 13–11
Run ModelSim 13–12
Usage . 13–12
Design Example 13–12
Run Quartus II 13–12
Usage . 13–12
Design Example 13–13
Scale . 13–13
Parameters . 13–13
Port Interface . 13–14
Updated Help 13–15
Design Example 13–15
Signals . 13–15
Parameters . 13–15
Updated Help 13–16
Design Example 13–16
Chapter 14. FFT Library
Dual Twiddle Memory (DualTwiddleMemoryC) . 14–1
Parameters 14–2
Port Interface 14–2
Edge Detect (EdgeDetect) 14–2
Parameters 14–2
Port Interface 14–3
Negate 14–3
Parameters 14–3
Port Interface 14–3
Negate Parameterizable . 14–4
Pulse Divider (PulseDivider ) 14–4
Parameters 14–4
Port Interface 14–4
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DSP Builder Handbook November 2012 Altera Corporation
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Pulse Multiplier (PulseMultiplier) 14–4
Parameters 14–4
Port Interface 14–5
Butterfly I C (BFIC) . 14–5
Parameters 14–5
Port Interface 14–5
Design Example . 14–6
Butterfly II C (BFIIC) 14–6
Parameters 14–6
Port Interface 14–6
Design Example . 14–7
Bit Reverse Core C (BitReverseCoreC) . 14–7
Parameters 14–7
Port Interface 14–7
Design Example . 14–7
Bit-Reverse FFT with Natural Output (FFT_BR_Natural) 14–7
Port Interface 14–8
Twiddle Generator (TwiddleGenC) . 14–8
Parameters 14–9
Port Interface 14–9
Design Example . 14–9
Chapter 15. Filter Library
FIR and CIC Filters . 15–1
Common Features . 15–1
Updated Help . 15–2
Basic FIR Filter Operation . 15–3
Half-Band and L-Band Nyquist FIR Filters 15–3
Automatic Pipelining . 15–3
High Speed Operation 15–4
Scalability . 15–4
Parameterization . 15–4
Coefficient Generation 15–4
Channelization 15–4
Decimating CIC 15–5
Features 15–5
Operation . 15–5
Parameters 15–6
Port Interface 15–6
Design Example . 15–6
Decimating FIR 15–7
Features 15–7
Operation . 15–7
Parameters 15–8
Filter Coefficients 15–9
Port Interface 15–9
Design Example . 15–9
Fractional Rate FIR 15–10
Features . 15–10
Operation 15–10
Parameters . 15–11
Filter Coefficients . 15–12
Port Interface . 15–12
Design Example 15–13
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Interpolating CIC 15–13
Features . 15–13
Operation 15–13
Parameters . 15–14
Port Interface . 15–14
Design Example 15–14
Interpolating FIR 15–15
Features . 15–15
Operation 15–15
Parameters . 15–16
Filter Coefficients . 15–17
Port Interface . 15–17
Design Example 15–17
Single-Rate FIR 15–18
Features . 15–18
Operation 15–18
Parameters . 15–18
Filter Coefficients . 15–19
Port Interface . 15–19
Design Example 15–20
Chapter 16. ModelBus Library
Bus Slave (BusSlave) 16–1
Parameters 16–1
Port Interface 16–2
Bus Stimulus (BusStimulus) 16–2
Parameters 16–3
Port Interface 16–3
Bus Stimulus File Reader (Bus StimulusFileReader) . 16–3
Parameters 16–4
Port Interface 16–4
Register Bit (RegBit) 16–5
Parameters 16–5
Port Interface 16–6
Design Example . 16–6
Register Field (RegField) 16–6
Parameters 16–6
Port Interface 16–7
Design Example . 16–7
Register Out (RegOut) 16–7
Parameters 16–7
Port Interface 16–8
Design Example . 16–8
Shared Memory (SharedMem) . 16–8
Parameters 16–8
Port Interface 16–9
Design Example . 16–9
Chapter 17. ModelPrim Library
Vector and Complex Type Support . 17–3
Vector Type Support . 17–3
Element by Element Mode 17–3
Mathematical Vector Mode . 17–4
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Interactions with Simulink 17–4
Complex Support 17–4
Restrictions . 17–4
Interactions with Simulink 17–5
Absolute Value (Abs) . 17–5
Parameters 17–5
Port Interface 17–6
Design Example . 17–6
Accumulator (Acc) . 17–6
Parameters 17–6
Port Interface 17–7
Design Example . 17–7
Add 17–8
Parameters 17–8
Port Interface 17–9
Design Example . 17–9
Add SLoad (AddSLoad) . 17–9
Parameters . 17–10
Port Interface . 17–10
Design Example 17–10
AddSub 17–11
Parameters . 17–11
Port Interface . 17–11
AddSubFused 17–11
Parameters . 17–11
Port Interface . 17–11
AND Gate (And) 17–11
Parameters . 17–12
Port Interface . 17–12
Design Example 17–12
Arc Cosine (ACos) (Deprecated) . 17–12
Parameters . 17–12
Port Interface . 17–13
Design Example 17–13
Arc Sine (ASin) (Deprecated) 17–13
Parameters . 17–13
Port Interface . 17–13
Design Example 17–13
Arc Tan (ATan) (Deprecated) . 17–13
Parameters . 17–14
Port Interface . 17–14
Design Example 17–14
Bit Combine (BitCombine) 17–14
Parameters . 17–14
Port Interface . 17–15
Design Example 17–15
Bit Extract (BitExtract) . 17–15
Parameters . 17–16
Port Interface . 17–16
Design Example 17–16
Bit Reverse (BitReverse) 17–16
Parameters . 17–17
Port Interface . 17–17
Design Example 17–17
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Channel In (ChannelIn) 17–17
Parameters . 17–17
Port Interface . 17–17
Design Example 17–18
Channel Out (ChannelOut) . 17–18
Parameters . 17–18
Port Interface . 17–19
Design Example 17–19
CmpCtrl . 17–19
Parameters . 17–19
Port Interface . 17–20
Complex Conjugate (ComplexConjugate) . 17–20
Parameters . 17–20
Port Interface . 17–21
Compare Equality (CmpEQ) 17–21
Parameters . 17–21
Port Interface . 17–21
Design Example 17–21
Compare Greater Than (CmpGE) 17–22
Parameters . 17–22
Port Interface . 17–22
Design Example 17–22
Compare Less Than (CmpLT) . 17–22
Parameters . 17–22
Port Interface . 17–22
Compare Not Equal (CmpNE) 17–23
Parameters . 17–23
Port Interface . 17–23
Constant (Const) 17–23
Parameters . 17–24
Port Interface . 17–24
Design Example 17–24
Convert 17–24
Parameters . 17–25
Port Interface . 17–26
Design Example 17–26
CORDIC . 17–26
Parameters . 17–27
Port Interface . 17–28
Cosine (Cos) (Deprecated) 17–28
Parameters . 17–28
Port Interface . 17–28
Design Example 17–28
Counter 17–29
Parameters . 17–29
Port Interface . 17–30
Design Example 17–30
Count Leading Zeros, Ones, or Sign Bits (CLZ) 17–30
Parameters . 17–30
Port Interface . 17–30
Dual Memory (DualMem) 17–31
Parameters . 17–31
Port Interface . 17–32
Design Example 17–32
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Demultiplexer (Demux) 17–32
Parameters . 17–33
Divide . 17–33
Parameters . 17–33
Port Interface . 17–33
Design Example 17–33
Exponent (Exp) (Deprecated) . 17–33
Parameters . 17–33
Port Interface . 17–34
Design Example 17–34
FIFO . 17–34
Parameters . 17–34
Port Interface . 17–35
Design Example 17–35
Floor (Deprecated) . 17–35
Parameters . 17–35
Port Interface . 17–36
Design Example 17–36
ForLoop 17–36
Port Interface . 17–36
Design Examples . 17–38
General Purpose Input (GPIn) . 17–38
Parameters . 17–38
Port Interface . 17–39
Design Example 17–39
General Purpose Output (GPOut) . 17–39
Parameters . 17–39
Port Interface . 17–39
Design Example 17–39
Load Exponent (LdExp) 17–39
Parameters . 17–40
Port Interface . 17–40
Design Example 17–40
Left Shift (LShift) 17–40
Parameters . 17–40
Port Interface . 17–41
Loadable Counter (LoadableCounter) 17–41
Look-Up Table (Lut) . 17–42
Parameters . 17–42
Port Interface . 17–43
Design Example 17–43
Loop . 17–43
Port Interface . 17–44
Design Examples . 17–44
Math 17–44
Parameters . 17–45
Port Interface . 17–45
Max and Min . 17–45
Parameters . 17–45
Port Interface . 17–46
MinMaxCtrl 17–46
Parameters . 17–46
Port Interface . 17–47
Modulus (Mod) (Deprecated) . 17–47
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Parameters . 17–47
Port Interface . 17–47
Design Example 17–47
Multiply (Mult) . 17–48
Parameters . 17–48
Port Interface . 17–48
Design Example 17–48
Multiplexer (Mux) . 17–49
Parameters . 17–49
Port Interface . 17–49
Design Example 17–50