Thạc Sĩ Designing an embedded system based on FPGA for image recognition

Introduction

Over the last ten years, a face recognition has been used in many specialized application areas within a larger field of a computer vision. This thesis introduces an algorithm, which is used for effective face recognition. It takes into consideration not only the face extraction but also the mathematical calculations that enable us to bring the image into a simple and technical form. Each image has a characteristic representation that eventually helps in the process of recognition. The algorithm is a principal component analysis (PCA). It is to reduce the dimensionality of a data set consisting of a large number of interrelated variables, while retaining as much as possible of the variation present in the data set. Face recognition systems usually consume a lot of time to match the face to its database constituents. This algorithm is used in the hardware to making the mathematical calculation faster. The algorithm uses new representations of the faces. The new representation is lesser space than the image. There are conveniences when we use FPGAs for this application. First, FPGAs are much smaller in size than computers. FPGAs can be easily integrated onto other systems. Second, FPGA systems consume less power than computer systems. Finally, FPGAs are easier to configure.

CONTENT

Acknowledgment . I
Introduction II
Thesis arrangement III
TABLE LIST VII
FIGURE LIST VII
Chapter 1: THE OVERVIEW OF THE FACE RECOGNITION ALGORITHM . 1
1.1 Overview . 1
1.2 Algorithms . 1
1.2.1 Neural Network . 1
1.2.2 Hidden Markov Model-HMM . 2
1.2.3 Principal Component Analysis (PCA) . 2
1.2.4 Linear Discriminant Analysis (LDA) 2
1.2.5 Independent Component Analysis (ICA) 3
1.3 The steps needed to perform a Principal Components Analysis . 3
1.4 Difficulties of real-time face recognition 5
1.5 Applications of face recognition . 6
Chapter 2: PRINCIPAL COMPONENT ANALYSIS . 7
2.1 Definition and derivation of principal components 7
2.2 Method used in PCA . 8
2.2.1 Statistics . 8
2.2.2 Standard Deviation 9
2.2.3 Variance . 9
2.2.4 Covariance . 9
2.2.5 The covariance Matrix . 10
2.2.6 Matrix Algebra . 10
2.2.7 Eigenvalues and Eigenvectors . 11
2.2.8 The steps of a Principal Components Analysis on a set of data 12
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Designing an embedded system based on FPGA for image recognition V
2.3 Application to Computer Vision . 16
2.3.1 PCA for Data Compression/Dimensionality Reduction Methods . 17
2.3.2 PCA to find patterns . 17
Chapter 3: SOPC BUILDER 18
3.1 Architecture of SOPC Builder Systems 18
3.2 System Interconnect Fabric for Memory-Mapped Interfaces . 19
3.3 Introduction to Avalon bus . 20
3.4 Avalon Memory-Mapped Interfaces . 20
3.5 Avalon Peripherals 21
3.5.1 Master Port . 22
3.5.2 Slave Port . 22
3.5.3 Avalon Slave Transfers 22
3.5.4 Avalon Master Transfers . 24
Chapter 4: DESIGNNING SOPC FOR FACE RECOGNITION . 27
4.1 The Algorithm used in the face recognition 27
4.2 The Database of Faces 27
4.2.1 AT&T database 27
4.2.2 Essex Grimace database 28
4.3 PCA Algorithm . 29
4.3.1 Training Phase . 29
4.3.2 Designing SOPC for the Face Recognition . 34
4.4 Designing a SD card controller . 35
4.4.1 SD bus protocol . 36
4.4.2 SD card data write . 37
4.4.3 SD card data read . 37
4.5 Designing a hardware accelerator for PCA . 38
4.5.1 The average matrix Block 38
4.5.2 Matrix multiplication Block 41
4.5.3 The squared Euclidian distance and the closest vector . 42
4.5.4 The system controller 44
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Designing an embedded system based on FPGA for image recognition VI
4.5.5 The square Euclidian distance . 47
4.5.6 Minimum value search circuit. 47
Chapter 5: EXPERIMENTAL RESULT OF PCA ALGORTHM ON THE HARDWARE . 51
5.1 Result on the software . 51
5.1.1 PCA algorithm on the software . 52
5.1.2 PCA+LDA algorithm on the software . 55
5.1.3 Some results on the software . 56
5.2 PCA algorithm on the hardware 59
5.2.1 The result of the design analysis and synthesis . 60
5.2.2 Some results on the hardware 62
5.3 The executing time on the hardware. 63
5.3.1 The SD Card system 64
5.4 Conclusion . 65
5.5 Development . 65
Reference: . 66