Báo Cáo A vlsi architecture for manhattan distances and wta

A vlsi architecture for manhattan distances and wta

A VLSI architecture for calculating Manhattan distances and finding the minimum value (Winner
Take All - WTA) has been designed to aim at image recognition and compression (using vector
quantization - VQ) applications. This architecture uses SIMD and two stages pipeline. The result is
tested on FPGA Stratix and its configuration can be changed easily. We do not develop any image
processing theory but just design the VLSI architecture for real time processing based on hardware.