Thạc Sĩ A soft error tolerant sram design in 130nm cmos technology

TABLE OF CONTENTS
Acknowledgement
Abstract
Table of contents
Abbreviations
List of tables
List of figures
CHAPTER 1 - INTRODUCTION 1
1.1. Problem and motivation .1
1.2. Contribution of the thesis .2
1.3. Thesis organization 2
CHAPTER 2 - BACKGROUND .4
2.1. Soft errors in semiconductor device .4
2.1.1. Radiation sources .4
2.2. Soft errors occurrence mechanism .5
2.3. Soft errors mitigation techniques .6
2.3.1. Device level techniques .6
2.3.2. Circuit level techniques .7
2.3.3. Block level techniques .7
CHAPTER 3 – SOFT ERROR TOLERANT SRAM DESIGN .10
3.1. SRAM specification .10
3.1.1. General information .10
3.1.2. Floorplan 11
3.1.4. Operation brief description 12
3.2. SRAM detail design .14
3.2.1. SRAM cell architecture .14
3.2.2. Replica path for Read operation 15
3.2.3. Internal clock generator .17
3.2.4. Write circuit .19
3.2.5. Decoder 19
3.2.6. Input/output latches 21
3.3. Error detecting and correcting (EDC) block 22
3.3.1. Hamming code algorithm 23
3.3.2. EDC block implementation .24
3.3.3. EDC detail architecture 26
CHAPTER 4 – DESIGN SIMULATION AND VERIFICATION 37
4.1. SRAM cell simulation 37
4.1.1. SRAM cell simulation to find device size .37
4.1.2. SRAM cell characteristic summary .42
4.1.3. Static noise margin comparison .43
4.1.4. SRAM cell capacitance 43
4.2. Soft error tolerant simulation .44
4.2.1. Verification methodology 44
4.2.2. Critical charge simulation 45
4.2.3. Simulation results 46
4.2.4. Conclusion .49
4.3. Post-layout simulation 50
4.3.1. Simulation setup 50
4.3.2. Cycle time definition and simulation result .52
4.3.3. Access time 55
4.3.4. Setup time 56
4.3.5. Timing delay of some critical paths .57
4.3.6. Simulation results summary 61
4.4. SRAM and EDC functional verification 61
4.4.3. Simulation setup 65
4.4.4. Functional verification result .67
4.5. Physical verification .70
CHAPTER 5 – CONCLUSION AND FUTURE WORK .75