Sách A CPLD VHDL Introduction _Application Note: CPLD

This introduction covers the fundamentals of VHDL as applied to Complex Programmable
Logic Devices (CPLDs). Specifically included are those design practices that translate soundly
to CPLDs, permitting designers to use the best features of this powerful language to extract
optimum performance for CPLD designs.
VHDL, an extremely versatile tool developed to aid in many aspects of IC design, allows a user
to structure circuits in many levels of detail. This versatility also makes the job of the VHDL
synthesis tool a lot more complex, and there is latitude for interpretation depending on the
VHDL coding style. One synthesis tool may implement the same code very differently from
another. In order to achieve the best results using VHDL, the designer should work at the
Register Transfer Level (RTL).
Although working at the RTL for designs may be more time-consuming, all major synthesis
tools on the market are capable of generating a clear cut implementation of designs for CPLDs
at this level. Using higher levels of abstraction may give adequate results, but tend to be less
efficient. Additionally, by expressing designs in this manner, the designer also gains the ability
to port VHDL designs from one synthesis tool to another with minimal effort. The following
examples will show designers the best design practices when targeting Xilinx XC9500XL,
XC9500XV and CoolRunnerTM XPLA3 families.
This application note covers the following topics:
ã Multiplexers
ã Encoders
ã Decoders
ã Comparators
ã Adders
ã Modeling Synchronous Logic Circuits
ã Asynchronous Counters
ã Finite State Machines

ã Coding Techniques
Multiplexers Multiplexers can be modeled in various ways. The four common methods are to:
1. Use an if statement followed by multiple elsif statements.
2. Usage of a case statement.
3. Conditional signal assignment.
4. Selected signal assignment
The example below shows the coding for a 1-bit wide 4:1 multiplexer.

There is no incorrect method of modeling a multiplexer. However, case statements require less
code than if statements. The conditional and selected signal assignments have to reside
outside a process. Therefore, they will always be active and will take longer to simulate.
One-bit Wide 4:1 Mux
library ieee;
use ieee.std_logic_1164.all;
--Comments are denoted by two - signs.
entity MUX4_1 is
port
(
Sel : in std_logic_vector(1 downto 0);
A, B, C, D : in std_logic;
Y : outstd_logic
);
end MUX4_1;
architecture behavior of MUX4_1 is
begin




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